Low Power Multiplier & Shifter Design
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 90 === This thesis presents a design methodology for the low power multiplier and the low power shifter. In the low power multiplier, the modified Booth architecture and the efficient sign extension can decrease the addition operation among partial products. By using f...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/35224197962087219363 |