Low Power Multiplier & Shifter Design

• Main Authors: Hao-Zhi Su, 蘇浩志
• Other Authors: Feipei Lai
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/35224197962087219363

碩士 === 國立臺灣大學 === 資訊工程學研究所 === 90 === This thesis presents a design methodology for the low power multiplier and the low power shifter. In the low power multiplier, the modified Booth architecture and the efficient sign extension can decrease the addition operation among partial products. By using fewer adders compared with the Braun-Wooley multiplier, the power consumption can be reduced. In order to enhance the performance of the multiplier, pipeline registers are inserted inside the multiplier to increase the throughput of the multiplier and Wallace tree 4:2 compressors are used to speed up the addition operation of partial products. According to the simulation results, using the MUX-based 4:2 compressor can increase the power saving ratio compared with the ADD-based one. In the low power shifter, the simulation results demonstrate that the logarithmic shifter consumes less power than the array shifter. So we use the logarithmic right shifter as the core of the fully functional barrel shifter, and insert additional stages and control circuits to achieve right rotation, logical/arithmetic right shifting, left rotation, and logical left shifting operations. Due to the fully functional barrel shifter is constructed by pass transistors, placing appropriate buffers is necessary. Based on the experimental results, the fully functional barrel shifter with three layers buffer of 1x size (W/L = 0.3/0.24) has less power consumption.