Research and Design on Clock and Data Recovery for 1.25Gbps Gigabit Ethernet Transceiver
碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === The transceiver is composed of a transmitter that serializes 10-bit parallel data and a receiver that deserializes serial data back into 10-bit parallel data. A clock and data recovery(CDR) circuit is one of the key components of optical receiver , wh...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33157637845475595805 |