Design and Application of a 1.25 Gb/s Clock and Data Recovery Circuit
碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === The goal of this work is to use a standard CMOS process to implement a 1.25 Gb/s dual-loop clock and data recovery (CDR) circuit. This thesis could be divided into five chapters. The chapter 1 is introduction. The chapter 2 starts with the basics of t...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/17810410561205232849 |