Design and Implementation of Multi-Stage Delta-Sigma Modulators
碩士 === 國立臺灣科技大學 === 電子工程系 === 90 === Oversampled analog-to-digital converters based on delta-sigma ( ) modulation are attractive for VLSI implementation because they are especially tolerant of circuit nonidealities and component mismatch. This thesis presents the design and implementation of a 4th o...
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| Format: | Others |
| Language: | zh-TW |
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2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25746314038468982714 |