LOW POWER HIGH PERFORMANCE CIRCUIT WITH TOLERANCE TO THRESHOLD VOLTAGE FLUCTUATION
碩士 === 大同大學 === 電機工程研究所 === 90 === In this thesis, we consider the high-speed operation of MOS transistors in the digital circuit, we analysis a new reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. We also use t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/32628611485399514357 |