LOW POWER HIGH PERFORMANCE CIRCUIT WITH TOLERANCE TO THRESHOLD VOLTAGE FLUCTUATION
碩士 === 大同大學 === 電機工程研究所 === 90 === In this thesis, we consider the high-speed operation of MOS transistors in the digital circuit, we analysis a new reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. We also use t...
Main Authors: | Jingn - Hong Li, 李璟泓 |
---|---|
Other Authors: | Ming-Chien Tasi |
Format: | Others |
Language: | zh-TW |
Published: |
2002
|
Online Access: | http://ndltd.ncl.edu.tw/handle/32628611485399514357 |
Similar Items
-
CMOS low-power threshold voltage monitors circuits and applications
by: Caicedo, Jhon Alexander Gomez
Published: (2016) -
CMOS low-power threshold voltage monitors circuits and applications
by: Caicedo, Jhon Alexander Gomez
Published: (2016) -
CMOS low-power threshold voltage monitors circuits and applications
by: Caicedo, Jhon Alexander Gomez
Published: (2016) -
An Improved Low Voltage/Low Power Multi-Threshold CMOS Digital Circuit Design
by: Jiann-Shing Shieh, et al.
Published: (1999) -
Effect of MOSFET threshold voltage variation on high-performance circuits
by: Narendra, Siva G. (Siva Gurusami), 1971-
Published: (2005)