The Core Module Design of a Digital Signal Processor for Embedded Architecture
碩士 === 元智大學 === 電機工程學系 === 90 === In this thesis, we propose a integrated DSP core design concept for a timing, functional and repeating product development with DHL language’s flexibility to design a programmable DSP core architecture. It uses fixed 16 bits to cope with the DSP character such as H...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/75920317938465316399 |