The Implemetation of Modified Discrete Fourier Algorithm by FPGA

• Main Authors: Chin-Lung Chen, 陳錦龍
• Other Authors: Chi-Shan Yu
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/67064194912641274843

碩士 === 國防大學中正理工學院 === 電子工程研究所 === 91 === The main purpose of this thesis is to use the Verilog Hardware Description Language cooperated with Matlab simulations to verify the Modified Discrete Fourier Transform (MDFT) Algorithm. Via the algorithm, the fundamental frequency Phasor can be calculated very fast. The thesis put emphasis in a synchronized Phasor Measurement Unit (PMU), which is applied to power systems, and whose function is to measure the phasor of fault current. For the fault current signals which contain the decaying DC component, it takes a long time for the conventional DFT algorithm to obtain the stable phasor of fundamental frequency. In order to compute the fundamental frequency phasor for the fault signals quickly after the fault occurs, this thesis adopted the MDFT algorithm proposed by Dr. Yu. The main purpose of this algorithm is to compute the decaying dc component of fault current signals and to remove it to get the accurate fundamental frequency phasor in relaying applications. The MDFT algorithm only needs “one cycle plus one samples” to find the accurate fundamental frequency phasor. Meanwhile, it also involves a new noise immunity phenomenon in this algorithm. In addition, when the decaying dc component disappears, the proposed algorithm will work as the conventional DFT. Thus, the proposed new algorithm is also robust. The proposed algorithm is tested via some test signals. Simulation results indicate that the proposed algorithm is accurate and effective. In the process of implementing the MDFT algorithm by FPGA, the first step is to compute the phasor of fundamental frequency of decaying dc component through Recursive DFT module. Then we design a correction module to remove the decaying dc component to obtain the accurate phasor of fundamental frequency. Finally, the CORDIC algorithm proposed by Kia Bazargan is used to compute the phasor of fundamental frequency. In the consequence, from the comparison between the simulation results of Verilog codes in QuartusII and those of MATLAB, it shows that the obtained fundamental frequency phasor is effective and accurate.