A Fast-Locking and Low-Jitter All Digital Delay Locked Loop
碩士 === 國立中正大學 === 電機工程研究所 === 91 === In this Thesis, a new Differential-Type Delay Cell is proposed. There four key features of this work, using differential loading to get (1) high resolution phase delay, (2) prevent of process and supply voltage violation. (3) This work has same architecture in bo...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22760655104631731033 |