Stress Analysis of Cu Chip Under Wire Bonding Process
碩士 === 國立中正大學 === 機械系 === 91 === In order to improve the IC performance, Cu chips which combined copper interconnects with Low-K dielectric material are the trend of future IC development. Due to the low mechanical properties of Low-K materials, the chips may fail during the wire bonding process. In...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/89451780870661356439 |