Stress Analysis of Cu Chip Under Wire Bonding Process

• Main Authors: Yi Tsung Tsai, 蔡貽宗
• Other Authors: D. S. Liu
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/89451780870661356439

碩士 === 國立中正大學 === 機械系 === 91 === In order to improve the IC performance, Cu chips which combined copper interconnects with Low-K dielectric material are the trend of future IC development. Due to the low mechanical properties of Low-K materials, the chips may fail during the wire bonding process. In this research, nonlinear dynamic Finite Element Method (FEM) software (ABAQUS/Explicit) is used as a simulation tool, the material properties of the gold ball is assumed properly, and a two-step load curve is proposed to modify the effect of bonding force and ultrasonic vibration. The final ball bond simulation results are validated well with experimental data. The validated FEM model is used during the bonding process to understand the stresses generated in the bonded device. The results shown that to increase the bonding force dose not effect on the peak value of the contact pressure. Select Cu pad can better reduce the stresses in the chip. Moreover, to design Cu chip with FSG and SiO2 layer can obtain less sinking value of the bonding pad.