| Summary: | 碩士 === 中華大學 === 資訊工程學系碩士班 === 91 === As the process technology advances into the deep-submicro age, the process and design progress makes system-on-a-chip (SoC) possible. To obtain high-quality chip performance, well-designed IPs have been used to reduced design time of a SoC chip. For the design integration of a SoC chip, an IP-based physical integration flow is considered to integer all the IPs into a single chip. The integration flow is mainly divided into area-driven non-slicing floorplan, sliceable transformation of a non-slicing floorplan, timing-driven interconnection optimization global routing and crosstalk-reduction-driven full-chip gridless routing.
In this paper, we focus on the study of full-chip routing integration and full-chip gridless routing approach on SoC physical integration. Basically, the routing approach is divided into safe routing ordering for a slicing floorplan, pseudo-pin assignment on T-type junction region, crosstalk-reduction-driven gridless channel routing and routing space arrangement for all the channel routing results. The routing approach has tested three industrial benchmarks, xerox, ami33 and ami49.The experimental results show that the proposed routing approach obtains effective routing results on full-chip routing integration. In addition, the crosstalk-reduction-driven approach reduces 40~50% multiple-pin net crosstalk on average and 10% chip crosstalk on average.
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