VLSI Circuit Design of Motion Estimation Unit for Full-Search Block-Matching

• Main Authors: Chun-Fu Lin, 林群富
• Other Authors: Shang-Chih Ma
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/nauat5

碩士 === 中原大學 === 電機工程研究所 === 91 === In this thesis, we propose a novel VLSI architecture for Motion Estimation Unit, including PE-array, Search Area Ram, Address Generation Unit, and Control Unit. Our architecture use full-search block-matching algorithm for block-matching. The Motion Estimation Unit have two processing modes: sequential and parallel modes. We perform the parallel mode so that the clock cycle can be reduced while retaining the I/O rate. In the sequential mode, both the clock cycle and I/O rate are reduced. However the clock cycle of the sequential mode is slightly higher than that of parallel mode. Another objective of this thesis is to reduce the size of RAM for search area. The advantage of the size reduction includes: (1)smaller number of pin-count. (2)lower average power. (3)simpler design for address generation unit and control unit.