Design and Implementation of Dual-mode DCT IP Core and Reconfigurable DSP Processor
碩士 === 國立中興大學 === 電機工程學系 === 91 === In this thesis, we propose a cost-effective 2-D Discrete Cosine Transform IP Core with reconfigurable datapath. The chip can process 8 × 8 block of video sequence. Even-odd decomposition is suitable for VLSI implementation. The architecture...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/69479246943881421764 |