Design of Low-Power Fully Parallel Quadruple Content-Addressable Memory (QCAM) Based on Pseudo-CMOS Logic Structure
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === This thesis presents a novel VLSI architecture for a fully parallel content- addressable memory with low-power, and high-speed features. This design is based on a proposed static pseudo-CMOS logic structure that not only improves the comparison speed of the CA...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54735405683980683736 |