A 5.8GHz CMOS Wireless LAN Receiver Front-end Circuit

• Main Authors: Chih-Hsun Lin, 林郅勳
• Other Authors: Tai-Haur Kuo
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/44282422411017395965

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === This thesis presents the design and implementation of a single-chip CMOS receiver for IEEE 802.11a wireless LAN application. For a monolithic implementation, the use of the Low-IF architecture alleviates the necessity of off-chip components, used for image-reject passive filtering. At the same time, DC-offset and self-mixing problems arising from direction-conversion architecture are avoided. The receiver is composed of three main blocks, single-ended low noise amplifier (LNA), down-conversion mixer and quadrature LC cross-coupled oscillator in a CMOS IC. In addition, a constant-gm bias circuit and a start-up circuit are built in. Single-ended input is adopted to avoid applying on-board single-to-differential converter (balun) and occupying larger chip area. Meanwhile a single-ended active Gilbert-cell mixer, which provides higher conversion gain and needs lower LO signal amplitude to turn on/off switch stage simply, is used in I/Q path to transfer RF frequency (5.8GHz) to intermediate frequency (30MHz). Finally, a quadrature LC oscillator is used to generate precise in-phase and high voltage-swing quadrature LO signal synchronously, furthermore, avoid I/Q mismatch effect. The whole receiver system is highly linear and tolerates large blockers. The overall noise figure is 16.27 dB and S11 is -15.3 dB. The conversion gain of the whole system is 21.7 dB and input-referred intercept point (IIP3) could be 31.48 dBm. The receiver is implemented in 0.25μm 1P5M mixed-signal CMOS technology and operated with 2.5V power supply. In addition, it consumes 41.1 mW of power and occupies 1.097x1.089 mm2 die area, including bonding pads.