Interface morphologies and electrical characteristic of bonded GaAs wafers

碩士 === 國立交通大學 === 材料科學與工程系 === 91 ===   In this study, direct wafer bonding technology was used to bond GaAs wafers .Before bonding, the organic solutions were only used to preserve native oxide layer. The annealing temperature, bonding type is our variables, the mechanical strength, elec...

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Main Authors: Cheng-Lun Lu, 盧正倫
Other Authors: Yew Chung Sermon Wu
Format: Others
Language:zh-TW
Published: 2003
Online Access:http://ndltd.ncl.edu.tw/handle/12513851294557854111
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spelling ndltd-TW-091NCTU01590482016-06-22T04:14:05Z http://ndltd.ncl.edu.tw/handle/12513851294557854111 Interface morphologies and electrical characteristic of bonded GaAs wafers 砷化鎵晶圓接合的界面型態及電性的探討 Cheng-Lun Lu 盧正倫 碩士 國立交通大學 材料科學與工程系 91   In this study, direct wafer bonding technology was used to bond GaAs wafers .Before bonding, the organic solutions were only used to preserve native oxide layer. The annealing temperature, bonding type is our variables, the mechanical strength, electrical characteristic and interface morphologies were investigated by different conditions.   The mechanical strength of bonded interfaces was measured by pull test.The minimum strength is presented at 600 degree. This is due to the morphologies of oxide layer become from continuous type to hemisphere type (discontinuous).From EDS and diffraction pattern of hemisphere region , it is composed of defects and amorphous substances. So the strength is very weak compared with other regions. The cracks often occurred here during pull test.   The I-V curves were depend on the dopant in GaAs wafers , the resistances of N-type GaAs bonded wafer at 850 degree is large than that was at lower temperature , this is due to the acceptor level which was induced by the diffusion of oxygen at high temperature .This would result in lower majority carrier (electron) ,and the slop of I-V curves could become small .On the other hand, the electrical properties of P-type GaAs bonded wafers are improved by the increase of annealing temperature .   The different bonded type (anti- or in phase) have some effects on electrical properties.In general, the in-phase bonded type has better electrical properties than anti-phase. The defects and oxide layer are more easily trapped by anti- phase bonded interface which is a barrier for carrier transportation. Yew Chung Sermon Wu 吳耀銓 2003 學位論文 ; thesis 0 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立交通大學 === 材料科學與工程系 === 91 ===   In this study, direct wafer bonding technology was used to bond GaAs wafers .Before bonding, the organic solutions were only used to preserve native oxide layer. The annealing temperature, bonding type is our variables, the mechanical strength, electrical characteristic and interface morphologies were investigated by different conditions.   The mechanical strength of bonded interfaces was measured by pull test.The minimum strength is presented at 600 degree. This is due to the morphologies of oxide layer become from continuous type to hemisphere type (discontinuous).From EDS and diffraction pattern of hemisphere region , it is composed of defects and amorphous substances. So the strength is very weak compared with other regions. The cracks often occurred here during pull test.   The I-V curves were depend on the dopant in GaAs wafers , the resistances of N-type GaAs bonded wafer at 850 degree is large than that was at lower temperature , this is due to the acceptor level which was induced by the diffusion of oxygen at high temperature .This would result in lower majority carrier (electron) ,and the slop of I-V curves could become small .On the other hand, the electrical properties of P-type GaAs bonded wafers are improved by the increase of annealing temperature .   The different bonded type (anti- or in phase) have some effects on electrical properties.In general, the in-phase bonded type has better electrical properties than anti-phase. The defects and oxide layer are more easily trapped by anti- phase bonded interface which is a barrier for carrier transportation.
author2 Yew Chung Sermon Wu
author_facet Yew Chung Sermon Wu
Cheng-Lun Lu
盧正倫
author Cheng-Lun Lu
盧正倫
spellingShingle Cheng-Lun Lu
盧正倫
Interface morphologies and electrical characteristic of bonded GaAs wafers
author_sort Cheng-Lun Lu
title Interface morphologies and electrical characteristic of bonded GaAs wafers
title_short Interface morphologies and electrical characteristic of bonded GaAs wafers
title_full Interface morphologies and electrical characteristic of bonded GaAs wafers
title_fullStr Interface morphologies and electrical characteristic of bonded GaAs wafers
title_full_unstemmed Interface morphologies and electrical characteristic of bonded GaAs wafers
title_sort interface morphologies and electrical characteristic of bonded gaas wafers
publishDate 2003
url http://ndltd.ncl.edu.tw/handle/12513851294557854111
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