| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 91 === In this thesis, an easy controlled and low-latency IEEE WLAN 802.11a transmitter and synchronization with low remaining CFO are presented. For the transmitter (packet composer), it contains nine main modules with each having a chip-enable signal to achieve the design goals as easy controlled. For the synchronization, burst timing estimation, carrier frequency offset (CFO) estimation, equalizer and additional phase correction are established. And a hardware design for timing estimation and CFO estimation is provided. Behavior simulation is done by ADS co-simulation and Matlab. FPGA verification and measurement has been done. For 802.11a transmitter, it can have desired result under 20 MHz clock rates that defined by 802.11a standard and so can the synchronization hardware. The equivalent gate counts under FPGA implementation are 146176 and 156063 for transmitter and timing synchronization.
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