SoC Software/Hardwaer Co-Verification System

• Main Authors: Wen-Chieh Huang, 黃文傑
• Other Authors: Chang-Jiu Chen
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/54208219538964776072

碩士 === 國立交通大學 === 電資學院學程碩士班 === 91 === As the semiconductor technology has made great progress, System-on-Chip has become the kernel technologies for integrating computer, consumer, and communication. In other words, a system, which consists of CPU cores like RISC or DSP, memories and other IPs, can be easily embedded into a chip. But to make a SoC product successful, we must take care of the integration of hardware and software. Thus, it is quite critical that to build the HW/SW co-verification environment with EDA tools, HW/SW co-design tools, and other technologies to shorten the development cycle of SoC. The HW/SW co-verification system utilizes EDA tools, the features of various IPs, and hardware simulators, combining with the fast software simulation to improve the testing flow and the simulation performance. In this thesis, we build a HW/SW co-verification environment with innovative methods to speed the HW/SW simulation performance by integrating Faraday's DSP core [8], the test benches, and the Seamless [1] tool. In our HW/SW co-verification system, the software part will execute the computation-intensive part and the hardware will be responsible for the signal communication. The experiments have shown that our HW/SW co-verification system have a great improvement in the simulation performance over 70 times than the traditional method.