Synchronous/Asynchronous 4-T SRAM Using Dual Threshold Voltage
碩士 === 國立中山大學 === 電機工程學系研究所 === 91 === 英文提要： Two different topics associated with their respective applications are proposed in this thesis. The first topic is focused on the implementation of a 4-Kb 500MHz 4-T CMOS SRAM using low-Vthn bitline drivers and high-Vthp latches. The storage of data is r...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10081186264260574324 |