Design of Buffering Mechanism for Improving Instruction and Data Stream
碩士 === 國立中山大學 === 電機工程學系研究所 === 91 === In the microprocessor system, the bandwidth problems of instruction stream and data stream are the main causes that limit the performance of the system. Although cache can effectively smooth this problem, the processor still needs more than one clock cycle to g...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95899446831387904910 |