Improving ILP with the Vectorized Computing Mechanism in VLIW DSP Architecture
碩士 === 國立中山大學 === 電機工程學系研究所 === 91 === In order to improving the performance for real-time application, current digital signal processors use VLIW architectures to increase the degree of instruction level parallelism (ILP). Two factors will limit the ILP, one is enough hardware resource for all para...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/58764251280206231113 |