| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 91 === Failure analysis (FA) and diagnosis of memory cores play a key
role in system-on-chip (SOC) product development and yield
ramp-up. Conventional FA based on failure bitmaps and the experiences of the FA engineers is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables the product to reach a profitable yield level as soon as possible.
We propose a fault pattern oriented failure analysis methodology based on failure patterns and functional fault models of semiconductor memories. Based on the proposed approach, we developed a systematic memory failure analysis framework ---the Failure Analyzer for MEmories (FAME).
FAME integrates the Memory Error Catch and Analysis (MECA) system and Memory Defect Diagnostics (MDD) system.
The fault-type based diagnostics approach used by MECA can improve the efficiency of the test and diagnostic algorithms.
The fault-pattern based diagnostics approach used by MDD further
improves the defect identification capability. FAME also comes with a Fault/failure pattern viewer for inspecting the failure patterns and fault patterns. Our proposed approach provides an efficient way to automatically narrow down the potential causes of failures and identify suspect defects more accurately. Defect diagnostics and FA can be accelerated during the memory product and yield improvement stage. Furthermore, an experiment has been done on an industrial case, demonstrating very precise results in a much shorter time as compared with the conventional way.
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