Design and Implementation of a 3.125-Gb/s Clock Data Recovery Circuit
碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === The goad of this work is to use a standard CMOS process to implement a 3.125-Gb/s dual-loop clock/data recovery circuit (CDR). This thesis could be divided into five chapters. Chapter 1 is introduction. The system and architectures of CDRs are describ...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91127941807823641281 |