Assertion-Based Verification under Verilog Environment
碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === With designs becoming increasingly complex, the scope and scale of verification requirements faced by system, ASIC, and SOC verification engineers have dramatically expanded. This has, in turn, resulted in traditional approaches to functional verifica...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37757606480625608523 |