Block and Input/Ouput Buffer Placement in Flip-Chip Design

• Main Authors: Chih-Yang Peng, 彭志洋
• Other Authors: Yao-Wen Chang
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/61649670636516290542

碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as well as the delay skew of the paths. In this thesis, we propose a hierarchical top-down method for the block and input/output buffer placement in flip-chip design. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the following two steps: the alternating and interacting global optimization step and the partitioning step. The global optimization step places modules based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the modules are divided into two groups according to their coordinates and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of modules, defined by the ratio of the total module area to the chip area. At last, we refine the placement by perturbing modules inside a subregion as well as in different subregions. Compared with the placement using the B*-tree alone, our method obtains significantly better results, with an average cost of only 48.4\% of that obtained by using the B*-tree alone.