Minimizing Coupling Jitter in Multiple Clock Networks

• Main Authors: MING-FU HSIAO, 蕭明富
• Other Authors: SAO-JIE CHEN
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/94422126303274728418

博士 === 國立臺灣大學 === 電機工程學研究所 === 91 === Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase coupling jitter, which may degrade significantly the system performance. Besides, in modern chip designs, there is usually more than one clock net, and sometimes even tens of them. It is therefore imperative to design clock topologies to prevent possible coupling jitter among them. In this Dissertation, we address the coupling jitter problem. We propose algorithms to design clock topology, perform routing minimizing effective coupling length, and size buffers to minimize jitter effect. The experimental results show a significant reduction of coupling jitter compared to the conventional clock tree synthesis which does not take into account the inter-clock coupling jitter effects.