Ultra Precision Grinding of Silicon Wafers

• Main Authors: Hung Yi Huang, 黃弘毅
• Other Authors: Ho. Z. Young
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/15301360032924188148

碩士 === 國立臺灣大學 === 機械工程學研究所 === 91 === Abstract Silicon wafers are most extensively used materials for IC substrates. A single crystal silicon ingot before taking the form of wafers must go through a series of machining processes including slicing, lapping, surface grinding, edge profiling, and polishing. A prime requirement of the processes is to produce extremely flat surfaces on workpieces up to 350 mm diameter. A total thickness variation (TTV) of less than 15 micrometers is strictly demanded by the industry for 0.18μm IC process. Further the surfaces should be smooth (< 10 nm Ra) and have minimum subsurface damage (< 10μm) before the final touch by etching and polishing. The end products should be crack free mirror surfaces with mico-roughness less than 1.8Å. However subsurface damages are usually accompanied in the grinding and lapping processes, which result in reduced strength of substrates and give adverse effects on IC properties. In this thesis, experimental observations are conducted to investigate various parameters on the surface and subsurface damage of ground silicon wafers. Different methods are attempted to examine and measure the subsurface damages. The initial results indicate that grit size of the grinding wheel, feedrate applied in the grinding process, and the rotational speed of the wafer are the key factors. It is suggested that the surface and subsurface damage can be reduced by controlling the grain depth of cut. In addition, a new method is proposed to investigate the critical depth of cut of wafer grinding and it was shown that the critical depth of cut is about 30 nm. The subsurface damage of lapped wafer is also investigated. Finally, the article made a comparison between wafer grinding and lapping in economical aspect.