Scramble System in the DVB-S TV system
碩士 === 國立臺灣科技大學 === 電子工程系 === 91 === In this paper we describe an FPGA based scramble system used in DVB-S TV system. We used Verilog HDL to design the core scramble codec and synthesis under Altera FPGA chip. The use of Verilog and prast-prototype capability of FPGA had made the design a...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78734937073343709058 |