Scramble System in the DVB-S TV system

• Main Authors: Chang Lin, Zhi, 張林智
• Other Authors: Shie, Mon-Chau
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/78734937073343709058

碩士 === 國立臺灣科技大學 === 電子工程系 === 91 === In this paper we describe an FPGA based scramble system used in DVB-S TV system. We used Verilog HDL to design the core scramble codec and synthesis under Altera FPGA chip. The use of Verilog and prast-prototype capability of FPGA had made the design and debug process easy. Since DVB-S is digital format by scrambling the signal, we had made a cost affordable conditional access (CA) system. To help the head-end system operator to manage the CA system, we also develop a user interface program. Also in DVB-S head-end system uses ASI high-speed interface, another achievement of our system is able to handle ASI to FPGA interface. Our contributive of this work, is to provide a simple yet effective CA system for Taiwan’s DVB-S head-end system operator, who can only choose from expensive foreign CA equipment manufacturer. This is first attempt in Taiwan.