Scramble System in the DVB-S TV system
碩士 === 國立臺灣科技大學 === 電子工程系 === 91 === In this paper we describe an FPGA based scramble system used in DVB-S TV system. We used Verilog HDL to design the core scramble codec and synthesis under Altera FPGA chip. The use of Verilog and prast-prototype capability of FPGA had made the design a...
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ndltd-TW-091NTUST4280122016-06-20T04:16:00Z http://ndltd.ncl.edu.tw/handle/78734937073343709058 Scramble System in the DVB-S TV system DVB-S電視擾碼系統 Chang Lin, Zhi 張林智 碩士 國立臺灣科技大學 電子工程系 91 In this paper we describe an FPGA based scramble system used in DVB-S TV system. We used Verilog HDL to design the core scramble codec and synthesis under Altera FPGA chip. The use of Verilog and prast-prototype capability of FPGA had made the design and debug process easy. Since DVB-S is digital format by scrambling the signal, we had made a cost affordable conditional access (CA) system. To help the head-end system operator to manage the CA system, we also develop a user interface program. Also in DVB-S head-end system uses ASI high-speed interface, another achievement of our system is able to handle ASI to FPGA interface. Our contributive of this work, is to provide a simple yet effective CA system for Taiwan’s DVB-S head-end system operator, who can only choose from expensive foreign CA equipment manufacturer. This is first attempt in Taiwan. Shie, Mon-Chau 許孟超 2003 學位論文 ; thesis 75 zh-TW |
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碩士 === 國立臺灣科技大學 === 電子工程系 === 91 === In this paper we describe an FPGA based scramble system used in DVB-S TV system. We used Verilog HDL to design the core scramble codec and synthesis under Altera FPGA chip. The use of Verilog and prast-prototype capability of FPGA had made the design and debug process easy. Since DVB-S is digital format by scrambling the signal, we had made a cost affordable conditional access (CA) system. To help the head-end system operator to manage the CA system, we also develop a user interface program. Also in DVB-S head-end system uses ASI high-speed interface, another achievement of our system is able to handle ASI to FPGA interface. Our contributive of this work, is to provide a simple yet effective CA system for Taiwan’s DVB-S head-end system operator, who can only choose from expensive foreign CA equipment manufacturer. This is first attempt in Taiwan.
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author2 |
Shie, Mon-Chau |
author_facet |
Shie, Mon-Chau Chang Lin, Zhi 張林智 |
author |
Chang Lin, Zhi 張林智 |
spellingShingle |
Chang Lin, Zhi 張林智 Scramble System in the DVB-S TV system |
author_sort |
Chang Lin, Zhi |
title |
Scramble System in the DVB-S TV system |
title_short |
Scramble System in the DVB-S TV system |
title_full |
Scramble System in the DVB-S TV system |
title_fullStr |
Scramble System in the DVB-S TV system |
title_full_unstemmed |
Scramble System in the DVB-S TV system |
title_sort |
scramble system in the dvb-s tv system |
publishDate |
2003 |
url |
http://ndltd.ncl.edu.tw/handle/78734937073343709058 |
work_keys_str_mv |
AT changlinzhi scramblesysteminthedvbstvsystem AT zhānglínzhì scramblesysteminthedvbstvsystem AT changlinzhi dvbsdiànshìrǎomǎxìtǒng AT zhānglínzhì dvbsdiànshìrǎomǎxìtǒng |
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