Design and Implementation of Low-Power GHz CMOS Half-Digital PLL and High-Driving Digital Buffer
博士 === 淡江大學 === 電機工程學系 === 91 === Decreased power dissipation and transient voltage drops in CMOS power distribution networks are important for high-speed deep submicrometer CMOS integrated circuits. In this paper, three CMOS buffers based on the charge-transfer, split-path and bootstrapped techniqu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14202165054135478455 |