Design of Delay-Locked Loop with Fast-Lock and Wide-Range Operation
碩士 === 淡江大學 === 電機工程學系 === 91 === As the speed performance of VLSI systems increases rapidly, more emphasis is placed on suppressing skew and jitter in the clocks. Phase-locked loops (PLL’s) and delay-locked loops (DLL’s) have been typically employed in microprocessors, memory interfaces, and commun...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10452358257501866699 |