A Fast-Lock Low-Jitter CMOS Phase-Locked Loop Design and It’s BIST Study
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 91 === Phase-lacked loops (PLL) are widely used for clock phase synchronization, frequency synthesis, and mobile communication systems, data transfer systems, clock distribution in ASIC, SOC and microprocessor applications. It is very important and requisite in...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/89049707079136169762 |