Infrastructure of a Formal Verification Platform for SoC
碩士 === 國立中正大學 === 資訊工程研究所 === 92 === How to ensure that the functionality is correct in a System-on-Chip (SoC) chip is a troublesome issue. Because SoC is so complex that it becomes difficult to detect errors, especially in corner cases. Bugs may even exist after detailed simulation or emulation. In...
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59769835556782868330 |