Adaptive way configurable architecture for low power cache
碩士 === 國立中正大學 === 資訊工程研究所 === 92 === Microprocessor performance has been improved by increasing not only the size of on-chip caches but also the way set-associative of on-chip caches. However, that increases the total power consumption. When the increasing of use of portable computing sys...
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44078928277872530410 |