Analysis and Design of High-Speed and Low-Power CMOS Content-Addrdynamicessable Memories
碩士 === 國立中正大學 === 電機工程研究所 === 92 === In this paper, a new match-line scheme for the parallel Content-Addressable Memory (CAM) is proposed. Basically, the match circuit is constructed with the newly proposed pseudo-footless clock-and-data precharged dynamic (PF-CDPD) AND gates. Because of...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24155512570961252732 |