| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 92 === In this paper, a new match-line scheme for the parallel Content-Addressable Memory (CAM) is proposed. Basically, the match circuit is constructed with the newly proposed pseudo-footless clock-and-data precharged dynamic (PF-CDPD) AND gates. Because of the AND-type circuit structure, the switching activity and the corresponding power consumption of the match circuit are significantly reduced. The pseudo-footless effect in the PF-CDPD logic circuit results in high speed, even the bit width of the CAM array is as large as 128bits. After removing the charge-sharing problem in the dynamic circuit, the PF-CDPD match circuit permits utilization of the full inherent speed of gates, and is robust to the PVT variations. We also design a split-path match circuit to enhance the pseudo-footless effect to improve the search speed. A low-power and a high-speed 256x128 0.18-m 1.8-V PF-CDPD CAM macros have been implemented to prove the proposed design techniques. The high-speed PF-CDPD CAM has the shortest search time of 1.98ns compared to the data with published literature. When normalization is taken to the 0.13-m 1.2-V technology, the low-power PF-CDPD CAM macro has the world lowest energy-efficient record of 0.88 fJ/bit/search.
|
|---|
