Hierarchical Timing-Constrained Full-Chip Routing System
碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === As VLSI technology reaches deep submicron or nano-meter dimensions, VLSI design has become more complicated. In physical design, more different goals will come out in the routing stage, for example interconnect delay, routability, signal integrity…etc....
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/57956555612841469616 |