HDBL(Hierarchical Double-Bound List):A Multilevel Floorplan Representation for Large-Scale Modules
碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === The concept of IP modules and buffers is widely used in SOC design, and it is a bottleneck for large-scale design. In physical design, floorplanning is an important step, because the area, delay and routability of one chip are effected. Recently, modern floorpla...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/63162718493293354982 |