| Summary: | 碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === The concept of IP modules and buffers is widely used in SOC design, and it is a bottleneck for large-scale design. In physical design, floorplanning is an important step, because the area, delay and routability of one chip are effected. Recently, modern floorplan algorithms can not obtain a better result to satisfy the requirement in large-scale VLSI design. The contribution of this paper is to develop one multilevel floorplan methodology to handle large-scale design. In the multilevel floorplan, it will use a HDBL(Hierarchical Double-Bound List) representation that based on DBL(Double-Bound List) representation to represent one floorplan and propose the simulated-annealing-based(SA-based) method to refine the multilevel floorplan result.
The SA-based floorplan approach based on HDBL can be divided into two steps: Clustering and Declustering. The clustering step will group iteratively the circuit modules into one virtual module until one virtual module includes all of the physical modules. After the clustering step, the HDBL representation will be obtained for the given floorplan. Based on HDBL, our proposed SA-based floorplan approach, uses five effective perturbation operations, Rotate, Move I, Move II, Swap I and Swap II, to obtain a better floorplanning result in the declustering step.
The experiment results show that our SA-based floorplan approach on HDBL can improve the initial floorplan effectively.
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