Congestion-Driven Floorplan on DBL Representation

碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === As VLSI technology reaches deep-sub micron dimensions and the application of SoC (System-on-Chip) design is general, the scale of VLSI circuit becomes more complex. A traditional area-driven floorplan become less import...

Full description

Bibliographic Details
Main Authors: Chien-Chen Su, 蘇乾禎
Other Authors: Jin-Tai Yan
Format: Others
Language:zh-TW
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/31823566479877559331