| Summary: | 碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === As VLSI technology reaches deep-sub micron dimensions and
the application of SoC (System-on-Chip) design is general,
the scale of VLSI circuit becomes more complex. A traditional
area-driven floorplan become less important because of the
decrease in cost of chip area. In floorplan stage, it is
necessary for a successful chip design to develop an effective
congestion analysis before global routing base on floorplan or
placement information.
To deal with multi-objective floorplan issue, we proposed
double-bound-list (DBL) representation. DBL representation is
more advanced than other representations (Ex. sequence pair,
O-tree and B*-tree) and conform to the property of P-admissible
because we can find out the total area and the adjacent relation between blocks with less memory. We also proposed hierarchical stair contour as our data structure to record the contour of floorplan and reduce the time complexity of data searching. In order to handle routability problem efficiently, hierarchical quad-grid model is proposed to estimate congestion. Quid-grid partition depend on wire density to avoid less accurate and more timing-consuming in 2-D static uniform grid-based model.
A floorplan with congestion estimation before routing stage can reduce time complexity of routing procedure. The experimental results show that the method we proposed can decrease routing congestion with a few penalties for chip area.
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