Design of a Floating-point Multiplication/Division-Addition Fused Unit
碩士 === 逢甲大學 === 資訊工程所 === 92 === This thesis presents a design of an IEEE floating-point multiplication/division add fused unit. The design of the unit is based on the design of a multiplication-add fused unit (MAF). We integrated a multiplicative division algorithm into our unit and adopted a new “...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/55614700772824063040 |