| Summary: | 碩士 === 逢甲大學 === 資訊工程所 === 92 === This thesis presents a design of an IEEE floating-point multiplication/division add fused unit. The design of the unit is based on the design of a multiplication-add fused unit (MAF). We integrated a multiplicative division algorithm into our unit and adopted a new “two-step normalization algorithm” normalization for floating-point multiplication and division. This unit is divided into four stages. The function of the first stage performs the first step of division. The second stage includes the alignment of the exponents, addition and combination of multiplication and the second step of the division. The third stage includes the first normalization and the decision of final sign value. In the fourth stage, second normalization and rounding are performed according to the IEEE 754 standard. Our research is to study how to add division function into an MAF unit and save the cost of the hardware. After analyzing the relationship between the exponent’s difference of the operands and the leading zero number, we modify the architecture of the MAF unit with two-step normalization algorithm. The modified unit can make multiplication-add and division-add share the same normalization and rounding circuits. Moreover, this modification can reduce the conventional three-word-length mantissa adder into a two-word-length adder. We have designed the proposed unit in VHDL. The designed unit has been tested by using a testbench written in Verilog and verified by simulations on ModelSim software. In conclusion, the inclusion the division operation into the MAF unit does not decrease on the speed of the multiplication-and-addition operation. The hardware cost of the floating-point MAF unit can a floating-point divider is reduced 16 percent by using our divider/multiplication fused unit design approach.
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