Programmable Arbiter Design for SoC Application
碩士 === 義守大學 === 電子工程學系 === 92 === In order to obtain high bandwidth utilization and low latency for on-chip bus communication, a hybrid arbitration algorithm and a programmable arbiter architecture are described in this thesis. The hybrid arbitration algorithm contains static fixed priori...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31696095258507373392 |