A New High-speed and Low-power Double Edge-Triggered D Flip-Flop
碩士 === 國立中興大學 === 電機工程學系 === 92 === Abstract In this thesis, a new high-speed and low-power CMOS double-edge-Triggered D flip-flop (DETDFF) is proposed. It consists of two parts. One is 4T/6T dual pulse generator and another one is a dual pulse data latch. The proposed Dual Pul...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60151624402542965327 |