A New High-speed and Low-power Double Edge-Triggered D Flip-Flop

• Main Authors: Yen Chao Wang, 王硯昭
• Other Authors: Robert Chen-Hao Chang
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/60151624402542965327

碩士 === 國立中興大學 === 電機工程學系 === 92 === Abstract In this thesis, a new high-speed and low-power CMOS double-edge-Triggered D flip-flop (DETDFF) is proposed. It consists of two parts. One is 4T/6T dual pulse generator and another one is a dual pulse data latch. The proposed Dual Pulse Data Latch (DPDL) uses and as the trigger signals to latch. The DPDL uses only six transistors with 2 transistor be clocked. Otherwise, A separate and for a trigger signal to the DPDL is used, the DPDL is suitable for the design of the divider and prescaler circuits. The DETFF is designed by using the TSMC 0.18um single poly six metal CMOS technology. The HSPICE simulation results show that the operating speed and the power consumption of the DETDFF are 2.3GHz and 945uW, 2.0GHz and 675uW, and 83.33MHz and 1.88uW when the supply voltage of 2.0V, 1.8V and 0.6V, respectively. Moreover, the proposed DPDL can be applied in the frequency divider circuit. Simulation results show that the operating speed and the power consumption of the divided—by-2 circuit are 6.0GHz and 219.5uW, 5.26GHz and 162uW, and 23.2MHz and 46uW under the supply voltage of 2.0V, 1.8V, and 0.5V, respectively. Therefore, the proposed circuits are very suitable for low-power and high-speed CMOS VLSI applications