| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === The most commonly used DFT technique for cell-based circuits is the scan-based design. However, because a typical ASIC today may contain more than one million logic gates, the test time and test volume have become two major concerns of the system-on-a-chip (SOC) testing. Advanced Scan Architecture (ASA) based on the previously developed input reduction method and a new zero aliasing output reduction method can significantly reduce the length of the necessary scan chain length with no fault coverage sacrificed for reducing the test time and test volume. However, the test development time and the manual error probabilities may increase if there is no design automatic tool to aid the designers to insert the test architecture. In this thesis, a design automatic tool is developed to insert the ASA into the circuits, to provide the test patterns and verification environment for this architecture, and to analyze the input reduction and output reduction. The developed tool includes the command mode and GUI operations. The main advantages of the design automatic tool are slashing the test development time, eliminating the manual mistakes, improving the productivity and test quality, and reducing test cost.
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