Video Codec Optimization for Dual-core Architectures

• Main Authors: Chien-Tang, Tseng, 曾建堂
• Other Authors: Chun-Jen, Tsai
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/76891445838942839978

碩士 === 國立交通大學 === 資訊工程系所 === 92 === In this paper, we propose a dynamic task partitioning framework on dual-core architecture (RISC and DSP) for the MPEG-4 Simple Profile video codec. Using a dynamic task scheduler, an efficient dynamic partitioning framework of video encoder algorithm on dual-core architecture are developed. Existing practices of embedded software development on a dual-core platform either assign a subtask to the RISC core or the DSP core. However, since new generations of RISCs are powerful enough for computationally intensive task as well, the proposed framework will invoke both the RISC and the DSP cores in parallel to complete a single subtask in a tightly-coupled manner. To alleviate the communication overhead between the two cores, DMA is used to transfer data between the MCU and the DSP. From the experiments, it is shown that the proposed approach achieves higher performance than the conventional approach where only one of the cores (either MCU or DSP) is used for each subtask.